LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ADDER IS 
    PORT(
    CIN, A, B: IN STD_LOGIC ;
    S, CO : OUT STD_LOGIC);
END ADDER;

ARCHITECTURE RTL OF ADDER IS 
    SIGNAL S1,S2,CO1,CO2: STD_LOGIC;
    COMPONENT HALF_ADDER 
    PORT(
        A, B : IN STD_LOGIC;
        SUM, CO : OUT STD_LOGIC);
    END COMPONENT;
BEGIN 
    CO <= CO1 OR CO2;
    S <= S2;
    U1: HALF_ADDER PORT MAP(A=>A,B=>B,SUM=>S1,CO=>CO1);
    U2: HALF_ADDER PORT MAP(CIN,S1,S2,CO2);
END RTL;